搜搜做题作业网英语翻译HD74HC5958-bit Shift Register/Latch (with 3-state output
来源：学生作业帮 编辑：搜搜做题作业网作业帮 分类：英语作业 时间：2024/07/27 02:27:21
英语翻译
HD74HC595
8-bit Shift Register/Latch (with 3-state outputs)
Description
This device each contains an 8-bit serial-in,parallel-out shift register that feeds an 8-bit D-type storage
register.The storage register has parallel 3-state outputs.Separate clocks are provided for both the shift
register and the storage register.The shift register has a direct-overriding clear,serial input,and serial
output pins for cascading.
Both the shift register and storage register clocks are positive-edge triggered.If the user wishes to connect
both clocks together,the shift register state will always be one clock pulse ahead of the storage register.
Features
* High Speed Operation:tpd (RCK to Q) = 17 ns typ (CL = 50 pF)
* High Output Current:Fanout of 15 LSTTL Loads (QA to QH outputs)
* Wide Operating Voltage:VCC = 2 to 6 V
* Low Input Current:1 μA max
* Low Quiescent Supply Current:ICC (static) = 4 μA max (Ta = 25°C)
Function Table
RCK SCK SCLR G Function
XXXHQ to Q high impedance
A H
X X L X Shift register cleared Q ’ = L
H
X H X Shift register clocked Q = Q ,Q = SER
n n – 1 A
X H X Contents of shift register transferred to output latches
HD74HC595
8-bit Shift Register/Latch (with 3-state outputs)
Description
This device each contains an 8-bit serial-in,parallel-out shift register that feeds an 8-bit D-type storage
register.The storage register has parallel 3-state outputs.Separate clocks are provided for both the shift
register and the storage register.The shift register has a direct-overriding clear,serial input,and serial
output pins for cascading.
Both the shift register and storage register clocks are positive-edge triggered.If the user wishes to connect
both clocks together,the shift register state will always be one clock pulse ahead of the storage register.
Features
* High Speed Operation:tpd (RCK to Q) = 17 ns typ (CL = 50 pF)
* High Output Current:Fanout of 15 LSTTL Loads (QA to QH outputs)
* Wide Operating Voltage:VCC = 2 to 6 V
* Low Input Current:1 μA max
* Low Quiescent Supply Current:ICC (static) = 4 μA max (Ta = 25°C)
Function Table
RCK SCK SCLR G Function
XXXHQ to Q high impedance
A H
X X L X Shift register cleared Q ’ = L
H
X H X Shift register clocked Q = Q ,Q = SER
n n – 1 A
X H X Contents of shift register transferred to output latches
HD74HC595
8位元移位寄存器/锁存器（ 3态输出）
描述
该器件每个包含一个8位串行的,并行输出移位寄存器,用户的8位D型存储
注册.已登记的存储并行三态输出.提供独立的时钟都转变
登记和储存登记.该移位寄存器的直接压倒一切清楚,串行输入和串行
输出引脚的级联.
两个移位寄存器和存储寄存器时钟是积极的前沿触发.如果用户希望连接
这两个时钟在一起,移位寄存器状态将永远是一个时钟脉冲领先的存储登记.
特征
*高速年份：脱附（ RCK至Q ） = 17纳秒典型（发光= 50电容）
*高输出电流：扇出15 LSTTL负载（质量保证,以青海产出）
*宽工作电压：虚拟通道连接= 2 6伏特
*低输入电流： 1微安最高
*低静态电源电流：国际刑事法院（静态） = 4微安马克斯（钽= 25 ℃ ）
函数表
RCK阴茎异常勃起SCLR G函数
XXXHQ至Q高阻抗
阿H
X X长X移位寄存器清除离散= L
H
x高x移位寄存器时钟频率为Q = Q表为Q =丝
ñ ñ - 1
XHX移位寄存器的内容转移到输出锁存
8位元移位寄存器/锁存器（ 3态输出）
描述
该器件每个包含一个8位串行的,并行输出移位寄存器,用户的8位D型存储
注册.已登记的存储并行三态输出.提供独立的时钟都转变
登记和储存登记.该移位寄存器的直接压倒一切清楚,串行输入和串行
输出引脚的级联.
两个移位寄存器和存储寄存器时钟是积极的前沿触发.如果用户希望连接
这两个时钟在一起,移位寄存器状态将永远是一个时钟脉冲领先的存储登记.
特征
*高速年份：脱附（ RCK至Q ） = 17纳秒典型（发光= 50电容）
*高输出电流：扇出15 LSTTL负载（质量保证,以青海产出）
*宽工作电压：虚拟通道连接= 2 6伏特
*低输入电流： 1微安最高
*低静态电源电流：国际刑事法院（静态） = 4微安马克斯（钽= 25 ℃ ）
函数表
RCK阴茎异常勃起SCLR G函数
XXXHQ至Q高阻抗
阿H
X X长X移位寄存器清除离散= L
H
x高x移位寄存器时钟频率为Q = Q表为Q =丝
ñ ñ - 1
XHX移位寄存器的内容转移到输出锁存
英语翻译HD74HC5958-bit Shift Register/Latch (with 3-state output
英语翻译1 SPICE deck for shift register simulation2 Shift regist
latch
英语翻译The R-S Flip-Flop.We can realize the latch function with
英语翻译Standby Rating:Output available with varying load for th
change with shift
failed to register with selling
英语翻译1st shift with 1 gang 06:00 hrs- 14:00 hrs in hatch 3 lo
英语翻译LATCH UP FREE OPERATION什么意思?
英语翻译The professor’s name didn’t register with the students.重
英语翻译Thank you for registration.I am glad to register with a
英语翻译In oreder to register with DIT you will need to attend t