英语翻译4)\x05Flow-Control Scheme:The flow control signal has to

英语翻译
4)\x05Flow-Control Scheme:The flow control signal has to fulfill the following requirements:
•\x05it has to be transmitted over a differential pair;
•\x05for AC coupling it has to be DC free;
•\x05it has to represent two states,receiver busy or ready.
We chose the flow control signal to be a square-wave because it is DC free and can easily be generated by clocked digital logic.The part of the FPGA which interfaces to the SerDes and performs the flow control is running at the same clock-speed as the parallel SerDes interfaces,e.g.125MHz for a 2.5Gbit/s link.The receiver FPGA signals that it is ready to receive by generating a square-wave at half its clock frequency,i.e.62.5MHz.If the receiver is running out of FIFO space it signals the sender to stop by generating a square-wave at an eighth of the clock frequency.
These signals can be easily decoded by the sender FPGA even though they are not synchronous to any of the sender FPGA's clock signals.It does so by counting the number of clock cycles the flow control signal keeps the same value.If this counter is one to three the sender keeps sending,if it counts to four or more the sender has to stop.
We have to know at what receiver FIFO fill-level we have to signal a stop condition to the sender.It is the sum of the forward channel and the back channel latency.According to [16] the SerDes has a total link latency of 38 + 107 = 145 bit times,giving 7.25 clock cycles,plus the line delay of the cable.
The flow-control back channel has a latency equal to the line delay plus two cycles for the synchronizer registers,plus 4 to 5 cycles to detect the stop state.This adds up to 14.25 cycles plus two line delays.
At a 2m maximum cable length this is 2 x 2m / 0.5c = 26.6 ns which is 3.3 cycles.2 Thus the total delay should be less than 18 cycles.The latest time to dispatch the flow control stop signal is thus when we have 18 words of the 16bit receiver FIFO remaining free.
5) 32bit word synchronization:When using 32bit addresses,two 16bit words have to be transferred per address.In order to detect the 32bit word boundary we define that the two 16bit words have to be sent back-to-back,with no IDLE characters in between.Once an IDLE character is seen,the receiver knows the 32bit word boundary.This allows 32bit words to also be sent back-to-back,once the receiver has seen a single IDLE character,thus the full bandwidth available can be used for address data.
D.FPGA implementation
We are using a Xilinx Spartan 3E series FPGA on the AEX board to link the three interface sections together.The PQ208 package chosen has a sufficient pin count for this system,while still allowing in-house assembly without reflow soldering.

4)\x05Flow-Control Scheme:The flow control signal has to fulfill the following requirements:
•\x05it has to be transmitted over a differential pair;
•\x05for AC coupling it has to be DC free;
•\x05it has to represent two states,receiver busy or ready.
We chose the flow control signal to be a square-wave because it is DC free and can easily be generated by clocked digital logic.The part of the FPGA which interfaces to the SerDes and performs the flow control is running at the same clock-speed as the parallel SerDes interfaces,e.g.125MHz for a 2.5Gbit/s link.The receiver FPGA signals that it is ready to receive by generating a square-wave at half its clock frequency,i.e.62.5MHz.If the receiver is running out of FIFO space it signals the sender to stop by generating a square-wave at an eighth of the clock frequency.
4.信息流控制方案：信息流控制信号必须符合下列要求：
* 信号必须通过一对差分线；
* 交流电的耦合必须没有直流；
* 它必须显示两种状态,接收器繁忙或准备接收.
我们选择的是方波信息流控制信号,因为它不需要直流且可以轻易由计时数字逻辑生成.与并串转换器连接和执行信息流控制的FPGA接口部件所运行的时钟速度是与并行接口一致的,例如2.5Gbit/s 的链接是125MHz.FPGA的接收器是以其时钟频率的一半生成方波信号表示已可接收信号,也就是62.5MHz.如果接收器已没有FIFO空间,它会用1/8的时钟频率生成方波信号通知发送器停止发信号.
These signals can be easily decoded by the sender FPGA even though they are not synchronous to any of the sender FPGA's clock signals.It does so by counting the number of clock cycles the flow control signal keeps the same value.If this counter is one to three the sender keeps sending,if it counts to four or more the sender has to stop.
We have to know at what receiver FIFO fill-level we have to signal a stop condition to the sender.It is the sum of the forward channel and the back channel latency.According to [16] the SerDes has a total link latency of 38 + 107 = 145 bit times,giving 7.25 clock cycles,plus the line delay of the cable.
尽管FPGA发送器没有与任何FPGA的时钟信号同步,但解码这些信号还是容易的.它是通过计算信息流控制信号维持同值的时钟周期数来实现的.如果周期数是一到三,发送器会继续发送信号,当达到四或以上时,发送器会停止发送.我们必须知道接收器的FIFO空间被装满至什么高度才应向发送器发送停止条件；这是前、后信道延时的总和.根据[16]中的串并转换器总共有链接时延38 + 107 = 145 位时间,有7.25个时钟周期,另加线缆的线路延时.
The flow-control back channel has a latency equal to the line delay plus two cycles for the synchronizer registers,plus 4 to 5 cycles to detect the stop state.This adds up to 14.25 cycles plus two line delays.
At a 2m maximum cable length this is 2 x 2m / 0.5c = 26.6 ns which is 3.3 cycles.Thus the total delay should be less than 18 cycles.The latest time to dispatch the flow control stop signal is thus when we have 18 words of the 16bit receiver FIFO remaining free.
信息流控制的后信道的时延是等于线路延时加同步注册器的2个周期,再加监测停止状态的四至五个周期,这合计达到14.25个周期加2个线路延时.
以最长2米的线缆计算,就是2 x 2m / 0.5c = 26.6 ns,即是3.3周期.因此,总延时应该低于18个周期.所以当16位接收器的FIFO空间只剩18字时,这是向信息流控制发送停止信号的最迟时间.
5) 32bit word synchronization:When using 32bit addresses,two 16bit words have to be transferred per address.In order to detect the 32bit word boundary we define that the two 16bit words have to be sent back-to-back,with no IDLE characters in between.Once an IDLE character is seen,the receiver knows the 32bit word boundary.This allows 32bit words to also be sent back-to-back,once the receiver has seen a single IDLE character,thus the full bandwidth available can be used for address data.
5.32位字同步：当使用32位地址时,每个地址必须转移两个16位字.为了检测32位字边界,我们的定义是,这两个16位字必须连续发送,中间不允许有IDLE字符.一旦有个IDLE字符被发现,接收器就知道32位字边界；这就让32位字也可以被连续发送,因此,全部的可用带宽能被用于地址数据.
D.FPGA implementation
We are using a Xilinx Spartan 3E series FPGA on the AEX board to link the three interface sections together.The PQ208 package chosen has a sufficient pin count for this system,while still allowing in-house assembly without reflow soldering.
D.运行FPGA
我们在AEX板上使用一个Xilinx Spartan 3E系列的FPGA将三个接口区连接起来.我们选择PQ208包是因为它有足够本系统使用的引脚数,而且不用再流焊就可进行内部组装.
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